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(Peer Reviewed, Referred & Indexed Journal)

Volume - 26 ** ISSUE - 1

Design and Analysis of Energy-Efficient High-Speed CMOS D Flip-Flops and Counters Employing Double-Gate F in FET Technology

A Divya Sai Lakshmi,E Bala krishna, Y L Ajay kumar
Pages: 1-7
DOI. No.

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Implementation and Analysis on FIFO using FPGA

A Roopa Sree,E Bala Krishna,Y. L. Ajay Kumar
Pages: 8-13
DOI. No.

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Design Space Exploration of Full Adder Circuits: A Power-Delay-Area Perspective Across CMOS Technology Scaling

A Nagendra Kumar,E. Balakrishna,Y. L. Ajay Kumar
Pages: 14-19
DOI. No.

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Performance Evaluation of a 4-bit Full Adder under power, Thermal, and Hardware Constraints Using Simulation Technique

C. Naga Krishna Pavan,G Aruna Kumari,Y.L Ajay kumar
Pages: 20-25
DOI. No.

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Design and Implementation of a Low-Power ALU for IoT-Based Embedded Systems

G Prasanna Tejaswini,G Aruna Kumari,Y. L. Ajay Kumar
Pages: 26-29
DOI. No.

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Design and FPGA Implementation of an Automated Bus Ticketing System Using Verilog HDL

G Niharika,C.Obulesu,Y. L. Ajay Kumar
Pages: 30-35
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Implementation of an XOR Based 16-bit Carry Select Adder for Area, Delay and Power Minimization

K CHANDU,T .G .Tejaswini,Y. L. Ajay Kumar
Pages: 36-39
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Design of the Adaptive LMS Filter For ECG Signal Noise Reduction

K Chandana Priya,N Swathi,T G Tejaswini
Pages: 40-47
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Design and Implementation of Image Encryption and Decryption Based on Reversible Logic Gates

M. Lakshmi Prasanna,T.Anusha,Y.L Ajay kumar
Pages: 48-53
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Performance Analysis of Full Adder using Different CMOS Technology

N Sindhusree,N.Swathi,T.G. Tejaswini
Pages: 54-58
DOI. No.

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Design and Analysis of a 1.28 mW K-Band Modified Gilbert-Cell Mixer Using 22 NM FDSOI CMOS

P. Shanthi,C.Obulesu,E.Balakrishna
Pages: 59-62
DOI. No.

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Performance Evaluation of Hybrid Fixed and Floating-Point PID Controller Architecture on Zynq-7000 FPGA

P.Revathi,Y.L Ajay kumar,E.Bala krishna
Pages: 63-68
DOI. No.

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Design of a Hybrid Multiplier-Based Optimized MAC Unit

R. Anitha Reddy,Y.L.Ajay kumar,C.Obulesu
Pages: 69-73
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DESIGN AND ANALYSIS OF OPTIMIZED BLOCK CIPHER DESIGN

Ravula Jayasree,Y.L Ajay kumar,G.Aruna kumari
Pages: 74-79
DOI. No.

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Design and Analysis of Efficient Clock-Gating Techniques for Power Management in Domino Logic Based Circuits Using 16-nm Technology

S H Vidya,E. Balakrishna2,Y. L. Ajay Kumar
Pages: 80-85
DOI. No.

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Design of RNS-KSA based 2D FIR Filter

S.Vamsi krishna,S.Salma,S.Sajida
Pages: 86-90
DOI. No.

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A Design of Low Power and High Speed Encoder and Decoder Circuits by Re-Evaluating High Speed Design Values

T.Ganesh Kumar Reddy,T.G Tejaswini,S.Salma
Pages: 91-96
DOI. No.

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Design and Comparison of Hysteresis Margin and Width in Schmitt Trigger Oscillators Implemented with Logic Gates in 28 nm CMOS

V.Manasa,S.Sajida,S.Salma
Pages: 97-100
DOI. No.

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Energy-Efficient Operational Transconductance Amplifier in CMOS for Bluetooth and Wi-Fi Applications

G Govindarajulu,B.Anantha Lakshmi,T.G. Tejaswini
Pages: 101-104
DOI. No.

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Design of a Low-Glitch Double-Edge Triggered Flip-Flop for Low-Power VLSI Systems

S. Kiran, S.Salma,T.G. Tejaswini
Pages: 105-109
DOI. No.

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Design and Implementation of a High-Performance Gated Voltage Level Translator with an Integrated Multiplexer

T Varalakshmi,N.Swathi,K Salma
Pages: 110-113
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Design of Speed–Area–Power Optimized Ternary Logic Gates Based on Standard MOS Technology

K Nagalakshmi,T Anusha,T.Sajida
Pages: 114-115
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Design of Low Power Current Steering DAC using 45nm CMOS Technology

E Sai Deepika,C.Obulesu,E.Balakrishna
Pages: 116-120
DOI. No.

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Design and Implementation of High-Speed, Low- Power CMOS D Flip-Flop and Counters using Double Gate FinFET Technology

V.Vidya Mayuri,T Anusha,B.Anantha Lakshmi
Pages: 121-126
DOI. No.

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Design and Analysis of Clock-Gated Domino Logic for Power Reduction in 16 nm CMOS

P Dilshad,K.Sajida,Y L Ajay kumar
Pages: 127-130
DOI. No.

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NON-LINEAR TRANSFORMATIONS AND WEAKLY SEMINORMED VECTOR SPACES: STRUCTURAL CHARACTERIZATION, STABILITY CONDITIONS, AND FUNCTIONAL IMPLICATIONS

P KRISHNA REDDY
Pages: 131-139
DOI. No. https://doi.org/10.64771/ijesat.2026.v26.i01.pp131-139

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INTEGRITY VERIFICATION & DATA SECURITY IN WIRELESS SENSOR NETWORKS

Mohammed Amaan Pasha,Mohammed Waheeduddin Hussain,Imtiyaz Khan
Pages: 140-149
DOI. No.

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AN EMPIRICAL ANALYSIS OF PRICING AND ADOPTION OF SUBSCRIPTION BUNDLES

Savanam Chandra Sekhar
Pages: 150-163
DOI. No. https://doi.org/10.64771/ijesat.2026.v26.i01.pp150-163

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MIND MAP-BASED PDF SUMMARIZER

Prakash Mali ,Viddesh Rahigude, Rajnish Kumar, Radhey Rokde, Shreyash Rajbanshi, Sanket Rajgude
Pages: 164-168
DOI. No. https://doi.org/10.64771/ijesat.2026.v26.i01.pp164-168

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MACHINE LEARNING-BASED FOREST FIRE PREDICTION MODEL UTILIZING UAV VIDEOS

G USHA SRI,K RAMYA MADHAVI
Pages: 169-177
DOI. No. https://doi.org/10.64771/ijesat.2026.v26.i01.pp169-177

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AUTOMATED IDENTIFICATION OF UNFORESEEN INCIDENTS UNDER CCTV SURVEILLANCE IN TUNNELS UTILIZING DEEP LEARNING

G USHA SRI,K RAMYA MADHAVI
Pages: 178-184
DOI. No. https://doi.org/10.64771/ijesat.2026.v26.i01.pp178-184

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DYNAMIC GENERATIVE RESIDUAL GRAPH CONVOLUTIONAL NEURAL NETWORKS FOR ELECTRICITY THEFT DETECTION

SITA SOWJANYA PRAKHYA,CH. SHYAMALA RANI,MATHANGI.VASUNDHARA
Pages: 185-191
DOI. No. https://doi.org/10.64771/ijesat.2026.v26.i01.pp185-191

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DIGITAL BELL WITH SCHEDULED SYSTEM

Rajabhau Thombare ,Poonam Musmade ,Rohan Talmure,Siddhi Lande, Prachi Patil, Shruti Raut, Premlata Sawant, Aditya Garad
Pages: 192-197
DOI. No. https://doi.org/10.64771/ijesat.2026.v26.i01.1985

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