Abstract :

This Paper Presents A Low-power, Low-voltage Down- Conversion Mixer Fabricated In A 22 Nm FDSOI CMOS Tech- Nology. The Proposed Mixer Design Is Based On Gilbert-cell Architecture And Uses A Passive Transformer Instead Of An Active Transconductance Stage To Overcome Voltage Headroom Limitations In Deep-sub-micron CMOS Technologies. Measurement Results Show That The Mixer Achieves A Voltage Conversion Gain Of 7.8 DB, An Input-referred 1 DB Compression Point Of -7 DBm, And IIP3 Of 4.8 DBm Under -8 DBm Local Oscillator Power. The Mixer Design Consumes A Low 1.28 MW Of Power From A Single 0.8 V Supply Voltage, Which Is A Significant Improvement Compared To The State-of-the-art. Furthermore, The Mixer’s Compact Size Of 0.54×0.45 Mm², Including Pads, Makes It A Highly Attractive Solution For Various Applications, As E.g. Radar. Index Terms—FDSOI CMOS, Down-conversion Mixer, Low Power, Low Voltage, Transformer, Linearity.

Published:

03-1-2026

Issue:

Vol. 26 No. 1 (2026)

Page Nos:

59-62

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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