Abstract :

Multiple Supply Voltages Are Commonly Used In De- Signs To Enable Better Power Performance Through Dedicated Con- Trol Of The Supply Voltage Of The Various Functional Units. In Multiple Supply Voltage Designs, Circuits Are Partitioned Into Voltage Islands That Operate At Their Optimum Supply Voltages Which Necessitates The Use Of Voltage Level Translators Between Them. This Paper Pre- Sents A High Performance Voltage Level Translator Design Aimed At Minimizing Insertion Penalty By Minimizing Logic Contention And Thereby Improving Latency. In Addition, The Proposed Voltage Level Translator Design Has An Integrated Logic Multiplexer Function Built In Through An Enable Signal. Simulation Results Of The Proposed Voltage Level Translator In Comparison With The Conventional Voltage Level Translator Shows Upto 42% Delay Reduction, Combined With A Power Benefit Upto 15%, For Supply Voltage Ranging From Nearthreshold To Above-threshold Levels. Keywords—Level Translator, Near-threshold, Abovethreshold, Multiple Supply Voltages, Logic Contention, Latency, Multiplexing.

Published:

03-01-2026

Issue:

Vol. 26 No. 01 (2026)

Page Nos:

110-113

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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