Abstract :

Wherever There Is A Need For Highperformance Computing Applications There Is An Evident Demand Of An Efficient High-speed Multiplier. Multiplication Takes Most Significant Time As Compared To Other Arithmetic Operations. Multipliers Are The Most Essential Blocks In Every High- Performance Computing Architecture Like Digital Signal Processing (DSP). MAC Unit Which Consist Of Multiplier And Accumulator Plays An Important Role To Decide The Performance Of Any DSP Block. The Better Performance Of MAC Unit Fulfills The Parameter Of Fast Computation And Real-time Processing Capabilities Of A DSP. Over The Years Number Of Ideas Have Been Proposed To Improve The Performance And Mitigate The Excessive Partial Product Term Generation During Conventional Multiplication Approach.In This Paper, We Have Focused On Proposing The MAC Architecture Using An Integrated Hybrid Binary Multiplier And Integrated CLA Adder Network. The Integrated Multiplier Is A Combination Of Karatsuba Algorithm And Urdhva Triyagbhyam Sutra From Vedic Mathematics. CLA Adder Network Consist Of CLA And Conditional Sum Adder Which Helps To Reduce Addition Time By Performing Parallel Addition. Mentioned Design Is Implemented In Verilog HDL Using Libero SOC PolarFire V2.1 Tool, Targeting Its PolarFire FPGA Family And MPF300T_ES- 1FCG484E Device. Keywords— DSP; MAC Unit; Karatsuba Multiplication Algorithm; Urdhva Triyagbhyam Sutra; CLA; Verilog HDL; FPGA

Published:

03-01-2026

Issue:

Vol. 26 No. 01 (2026)

Page Nos:

69-73

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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