Design And Analysis Of Efficient Clock-Gating Techniques For Power Management In Domino Logic Based Circuits Using 16-nm TechnologyID: 1958 Abstract : |
Published:03-1-2026 Issue:Vol. 26 No. 1 (2026) Page Nos:80-85 Section:Articles License:This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License. How to Cite |