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Design And Analysis Of Efficient Clock-Gating Techniques For Power Management In Domino Logic Based Circuits Using 16-nm Technology

S H Vidya,E. Balakrishna2,Y. L. Ajay Kumar

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ID: 1958

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Abstract :

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Published:

03-1-2026

Issue:

Vol. 26 No. 1 (2026)

Page Nos:

80-85

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

How to Cite

S H Vidya,E. Balakrishna2,Y. L. Ajay Kumar, Design and Analysis of Efficient Clock-Gating Techniques for Power Management in Domino Logic Based Circuits Using 16-nm Technology , 2026, International Journal of Engineering Sciences and Advanced Technology, 26(1), Page 80-85, ISSN No: 2250-3676.

DOI:

ISSN No:2250-3676 ----- Crossref DOI Prefix: 10.64771 ----- Impact Factor: 9.625