ISSN No:2250-3676 ----- Crossref DOI Prefix: 10.64771 ----- Impact Factor: 9.625
(Peer Reviewed, Referred & Indexed Journal)
Design Of Speed–Area–Power Optimized Ternary Logic Gates Based On Standard MOS TechnologyID: 1965 Abstract :Previous Papers Have Focused Solely On Designing Ternary Logic Gates Or Constructing Adders Using Predesigned Ternary Logic Gates. However, This Paper Takes A Novel Approach By Designing Ternary Logic Gates Using Typical MOSFETs And Employs Them To Construct A Ripple Carry Adder. Furthermore, This Paper Conducts A Comprehensive Comparison Between The Resulting Ripple Carry Adder And Binary Ripple Carry Adder In Terms Of Speed, Power(energy) Consumption, And Area. This Paper Demonstrates That The Ternary Adder Designed By The Author, Using PSpice And Verilog With VPI, Can Exhibit Differences 75% Compared To The Conventional Binary Adder. Keywords—ternary Logic Gates, Ternary Ripple Carry Adder, Speed, Power(energy) Consumption, Area |
Published:03-1-2026 Issue:Vol. 26 No. 1 (2026) Page Nos:114-115 Section:Articles License:This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License. How to Cite |