Abstract :

Dual Edge Triggered (DET) Methodology Is The Most Popular Preference For The Research Workers In The Field Of VLSI Designing Due To Its Low Power Consumption And Highperformance Quality. DET Methods Provide The Same Throughput At Half Of The Clock Frequency In Comparison With The Single Edge Triggered (SET) Methods. This Can Lessen The Half Power Consumption And Commit To Total System Power Savings. In This Paper, A Low Power Glitch Free Advanced Dual Edge Triggered Flip Flop (DETFF) Design Is Proposed. The Proposed Novel DETFF Is Constructed By Using The Combination Of C-element Circuit And 1P-2N Structure. If Any Error Affects One Of The Structure, Then It Is Nullified By The Other One Structure. To Limit The Input Burdening, The Two Circuits Are Combined To Contribute The Transistors Connected To The Input. This DETFF Has Used An Internal Dual Feedback Structure. The Presented DETFF Reduces The Area And Average Power Consumption And Gain The Higher Speed Of The System. Analysis Of The Temperature Impact On Power And Delay At Different Supply Voltages Has Also Been Done. Novel DETFF Is Implemented With 22nm CMOS Technology. Keywords: Clock Distribution Network; Dual Edge Triggered; Glitches; Power Consumption; Power Delay Product

Published:

03-1-2026

Issue:

Vol. 26 No. 1 (2026)

Page Nos:

105-109

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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