Abstract :

A Key Component Of Microprocessors, The Arithmetic And Logic Unit (ALU) Is In Charge Of Carrying Out All Arithmetic And Logic Operations Necessary For Computing. The Design And Performance Study Of A Unique 4-bit Reconfigurable ALU Utilizing Carbon Nanotube Field-Effect Transistor (CNTFET) Technology For Improved Efficiency In Very Large-Scale Integration (VLSI) Systems Are Presented In This Work. The Proposed Work Focuses On Optimizing Crucial Submodules Like The XOR Gate, 2x1 Multiplexer, And 4x1 Multiplexer At The Transistor Level Using Hybrid Logic Techniques In Order To Overcome The Drawbacks Of Conventional CMOS-based ALUs, Which Suffer From High Power Dissipation, Propagation Delay, And Area Constraints. The Suggested ALU Greatly Reduces The Number Of Transistors And Increases Efficiency While Maintaining The Architectural Benefits Of A Delay-controlled Reconfigurable ALU. HSPICE Is Used To Implement And Simulate The Design On 32 Nm CNTFET Technology. Significant Improvements In Power Consumption, Propagation Delay, Power Delay Product (PDP), And Energy Delay Product (EDP) Are Shown By Performance Evaluation. Compared To Current Designs, The Suggested Approach Reduces The Number Of Transistors By Around 27%, Improving Area Efficiency. The Suggested ALU Offers Complete Rail-to-rail Voltage Swing, Lower Latency, And Increased Energy Efficiency, According To Simulation Findings. As A Result, The Design Is Ideal For Next-generation Low-power, High-performance VLSI Applications, Especially In IoT-based And Portable Systems.

Published:

02-4-2026

Issue:

Vol. 26 No. 4 (2026)

Page Nos:

83-97

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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