Abstract :

Finite Impulse Response (FIR) Filters Play A Significant Role In Digital Signal Processing (DSP) Applications, Including Wireless Communication Systems, Biomedical Signal Processing, Audio And Speech Processing, Image Processing, Radar Systems, And Real-time Embedded Applications. So, The Work Is To Design The Reconfigurable Multi-Window Linear-Phase FIR (RMWLP-FIR) Architecture, Which Incorporates Reconfigurable Multi-window Processing, Symmetry Pairing, A Region-Aware Hierarchical Multiplier (RAHM), An Error-balanced Arithmetic Structure, And Pipelined Processing To Improve Resource Utilization, Control Arithmetic Complexity, And Reduce Power Consumption And Propagation Delay. The RMWLP-FIR Achieves The Lowest Reported Resource Utilization, Requiring 296 LUTs And 153 Flip-flops, While Recording A Setup Path Delay Of 25.450 Ns, A Hold Path Delay Of 0.358 Ns, A Calculated Combined Setup-plus-hold Delay Of 25.808 Ns, And Total Power Consumption Of 42.076 MW. Finally, The Proposed Architectural Progression Demonstrates The Potential Of Symmetry-based Computation, Coefficient Optimization, Configurable Window Processing, And Arithmetic Resource Sharing To Improve The Implementation Efficiency Of Linear-phase FIR Filters. Keywords: Digital Signal Processing, FIR Filter, Linear-phase Filter, Low-power Design, Multi-window Processing, Pipelined Architecture, Reconfigurable Architecture, Resource Optimization, Symmetry Pairing.

Published:

27-9-2026

Issue:

Vol. 26 No. 9 (2026)

Page Nos:

530-548

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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