Abstract :

This Paper Presents A Reference RTL Architecture That Integrates ML-KEM-768 And AES-128 In A Single Accelerator Accessible From A RISC-V System-on-chip Through An AXI4-Lite Interface. The Design Comprises A Keccak-f[1600] Permutation Core, A Centered-binomial Noise Sampler, An Iterative Numbertheoretic Transform (NTT/INTT) Engine, A Uniform Rejection Sampler, Compression/decompression Logic, A KEM Controller, And An Iterative AES-128 Core. Its Principal Architectural Feature Is A Hardware Path That Routes The ML-KEM Shared-secret Object Directly To The AES Key Input, So That Normal Operation Does Not Require Software To Read And Rewrite The Session Key. The AES Core Is Verified By An Encryption/decryption Round-trip Simulation; The ML-KEM Primitives Are Simulated Individually, And The Integrated Controller Is Exercised In An End-to-end Simulation. Complete ML-KEM Known-answer-test Validation, The Full Fujisaki–Okamoto Re-encryption Path, And Hardware Synthesis Results Are Not Reported, So The Cycle And Throughput Figures Are Architectural Estimates Rather Than Measurements. The Work Defines A Practical Hardware/software Boundary For Combining Post-quantum Key Establishment With Symmetric Encryption And Lists The Verification Steps Required Before Deployment.

Published:

27-10-2026

Issue:

Vol. 26 No. 10 (2026)

Page Nos:

148-153

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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