Abstract :

Reliable And High-speed Data Communication Is Increasingly Important In Modern Embedded Systems And System-on-Chip (SoC) Architectures, Where Multiple Peripheral Devices Operate Through A Shared Communication Bus. Although The Conventional Inter-Integrated Circuit (I2C) Interface Offers A Simple And Widely Adopted Solution, Its Limited Transfer Rate Restricts Its Suitability For Applications Requiring Higher Communication Throughput. The Inter-Integrated Circuit (I3C) Standard Addresses These Limitations By Providing Enhanced Data Transfer Performance Along With Features Such As Dynamic Addressing, In-band Interrupts, And Backward Compatibility With I2C Devices. This Work Presents The Design And Functional Verification Of An I3C Master Controller Incorporating High Data Rate–Double Data Rate (HDR-DDR) Communication Using Verilog HDL. The Proposed Design Is Organized Into Dedicated Modules For Clock Generation, Protocol Control Using A Finite State Machine, Frame Generation, HDR-DDR Data Transmission, Data Reception, And Bus Interfacing. In HDR-DDR Mode, Data Is Transferred On Both Rising And Falling Transitions Of The Clock, Allowing Two Data Transfers Within A Single Clock Cycle Without Requiring An Increase In The Operating Clock Frequency. The Controller Was Simulated, Functionally Verified, And Synthesized Using The Xilinx Vivado Design Environment To Evaluate Its Operational Correctness And Hardware Implementation Feasibility. The Obtained Results Demonstrate That The Proposed Architecture Can Support Efficient I3C Communication While Maintaining A Modular And Scalable Structure. The Design Can Serve As A Suitable Foundation For FPGA-based Embedded Communication Systems And Can Be Further Extended For Hardware Optimization And Future ASIC Implementation

Published:

14-10-2026

Issue:

Vol. 26 No. 10 (2026)

Page Nos:

42-47

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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