Abstract :

The Increasing Demand For Efficient Public Transportation Systems Has Created The Need For Intelligent And Automated Ticketing Solutions That Reduce Passenger Waiting Time, Eliminate Manual Ticket Handling, And Improve Operational Efficiency. Conventional Bus Ticketing Systems Mainly Rely On Conductors Or Electronic Ticketing Machines, Which Are Often Associated With Delays, Human Errors, Ticket Fraud, Inaccurate Fare Calculation, And Increased Operational Costs. As Urban Transportation Networks Continue To Expand, There Is A Growing Requirement For High-speed Digital Controllers Capable Of Performing Ticket Generation, Fare Calculation, Passenger Validation, And Transaction Management With Greater Reliability. Recent Advancements In Digital System Design, Field Programmable Gate Arrays (FPGA), Verilog Hardware Description Language (HDL), Embedded Systems, And Smart Transportation Technologies Have Enabled The Development Of Intelligent Hardware-based Ticketing Controllers With High Processing Speed And Low Power Consumption. This Project Presents The Design Of An Automatic Bus Ticketing System Controller Using Verilog HDL. The Proposed Framework Implements The Ticketing Controller Using Verilog HDL On An FPGA Platform, Integrating Passenger Input Modules, Destination Selection, Fare Calculation Logic, Digital Memory, LCD Display Interface, And Ticket Generation Unit Into A Unified Hardware Architecture. The Controller Continuously Receives Passenger Boarding Information, Calculates The Ticket Fare Based On The Selected Destination, Validates Payment, Generates Digital Ticket Information, And Updates Passenger Records In Real Time. The Hardware Implementation Provides Deterministic Execution, High-speed Processing, And Reliable Operation Compared With Conventional Software-based Ticketing Systems. Experimental Evaluation Demonstrates High Transaction Accuracy, Low Processing Delay, Reliable Ticket Generation, Efficient Fare Computation, And Stable FPGA Operation Under Different Operating Conditions. The Proposed Hardware Controller Significantly Improves Ticketing Efficiency, Minimizes Manual Intervention, Reduces Transaction Errors, Enhances Passenger Convenience, And Provides A Scalable And Cost-effective Solution For Modern Intelligent Public Transportation Systems. Keywords: Verilog HDL, FPGA, Automatic Bus Ticketing System, Digital Controller, Fare Calculation, Ticket Generation, Hardware Description Language, Finite State Machine (FSM), Smart Transportation, Embedded Systems.

Published:

06-8-2026

Issue:

Vol. 26 No. 8 (2026)

Page Nos:

731 - 739

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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