Abstract :

Hardware AES-128 Encryption Cores Conventionally Precompute And Store The Entire 44-word (1408-bit) Roundkey Schedule Before Encryption Begins, So That Every Rounds Key Material Is Available On Demand From A Wide Register Bank. This Paper Presents And Evaluates An Alternative Onthe-fly Key Expansion Architecture That Stores Only The Current Rounds Four Key Words (128 Bits) At Any Time, Regenerating The Next Rounds Key One Round Ahead Each Clock Cycle, With The Round Constant Supplied By A Galoisfield Linear-feedback-shift-register (LFSR) Recurrence In Place Of A Fixed Rcon Read-only-memory Table. Both The Existing Precomputed-schedule Design And The Proposed LFSR-based Design Are Captured In Verilog, Implemented In Xilinx Vivado 2019.2 Targeting The Artix-7 Part Xc7a100tcsg324-1, And Verified Bit-exact Against The FIPS197 Appendix B Known-answer Test Vector. Post-place-androute Results Under A 10.0 Ns Timing Constraint Show The Proposed Design Reduces Look-up-table Usage From 4133 To 1272 (-69.2%), Registers From 1682 To 403 (-76.0%), Onchip Power From 0.714 W To 0.121 W (-83.1%), And Criticalpath Delay From 8.204 Ns To 5.987 Ns (-27.0%), While Raising Throughput From 121.89 To 167.03 Mega-operations Per Second (+37.0%) And Cutting Energy Per Operation From 5857.656 PJ To 724.427 PJ (-87.6%). The Results Demonstrate That Shrinking Live Key-schedule Storage From 1408 Bits To 128 Bits Is A Structural, Not Incidental, Source Of Area, Power, And Energy Reduction In AES-128 VLSI Implementations.

Published:

27-7-2026

Issue:

Vol. 26 No. 7 (2026)

Page Nos:

1300-1309

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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