Abstract :

Multiplication Is The Most Power- And Delay-critical Operation In Digital Signal Processors, And The Multiplier Often Dominates Both The Energy Budget And The Critical Path Of An Arithmetic Unit. This Paper Presents The Design And Performance Evaluation Of A Low-power Multiplier Based On The UrdhvaTiryagbhyam (vertical-and-crosswise) Sutra Of Ancient Indian Vedic Mathematics, Described Entirely In VHDL. The Multiplier Is Built Hierarchically: A 2×2 Vertical-and-crosswise Core Is Used To Construct 4×4, 8×8 And 16×16 Blocks, So That All Partial Products Are Generated In Parallel And The Design Scales Regularly To Larger Widths. Because The Sutra Generates Every Partial Product Concurrently And Reuses Small Identical Blocks, The Number Of Logic Levels And The Switching Activity Are Reduced Relative To Conventional Array And Booth Multipliers, Which Is The Origin Of The Power Saving. The Design Was Coded In VHDL, Functionally Verified, And Synthesized For Evaluation Of Propagation Delay, Area And Dynamic Power Against Array And Booth Multipliers Of The Same Width. The Representative Results Reported Here Indicate Roughly A 40–45 % Lower Delay And A 30– 35 % Lower Dynamic Power Than A Conventional Array Multiplier, Giving A Substantially Lower Power–delay Product. All Numerical Values Are Illustrative And Should Be Reproduced With The Readers Own Synthesis And Simulation Data.

Published:

09-7-2026

Issue:

Vol. 26 No. 7 (2026)

Page Nos:

326-330

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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