Abstract :

The Current VLSI Systems Face Two Important Design Consideration Issues: Power Dissipation And Computation Speed, With The Increasing Demand For The Performance Of Portable Computing And Multimedia Devices. One Of The Most Important Arithmetic Components, Multipliers, Are A Considerable Contributor To The Overall Power Consumption And The Processing Time. In This Work, A Low Power And High Performance 8x8 Wallace Tree Multiplier With Changed Compressor Topologies Is Shown. The Proposed Method Uses The Optimised 4:2 And 5:2 Compressors Designed With The XORXNOR Logic And Multiplexer Assisted Structures For Better Efficiency Of Partial Product Reduction. The Architecture Is Designed To Reduce Switching Activity, Shorten The Critical Path And Enhance The Computational Performance While Keeping The Hardware Complexity Down. The Modified Wallace Reduction Stage Reduces The Partials Before Summing Them Up To Get The Final Sum. The Entire Design Has Been Written In Verilog HDL And Simulated Using Xilinx Vivado 2024.2. The Proposed Architecture Offers An Efficient Hardware Design Solution For High Speed And Low Power Applications With Multipliers In VLSI Systems.

Published:

01-7-2026

Issue:

Vol. 26 No. 7 (2026)

Page Nos:

34 - 39

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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