Abstract :

Machine Learning Accelerators Have Become Increasingly Important Due To The Rapid Growth Of Intelligent Edge Devices, With Global AI Hardware Deployments Expected To Exceed Billions Of Connected Systems And Real-time Data Generation Surpassing Hundreds Of Zettabytes Annually. However, Existing Dynamic Tsetlin Machine (DTM) Architectures Employ Deterministic Clause Evaluation, Classification, And Update Mechanisms, Which May Limit Learning Flexibility, Increase Unnecessary Parameter Updates, Reduce Robustness To Noisy Data, And Potentially Affect Generalization Performance When Handling Complex Datasets. To Address These Limitations, This Work Proposes A Probabilistic State Update-Dynamic Tsetlin Machine (PSU-DTM) Training Accelerator That Introduces Probabilistic Intelligence Into Both Learning And Inference Stages. The Proposed Architecture Consists Of A Feature Buffer, Partial Clause State Computation Unit, Clause Buffer, Probabilistic Weight Multiplication Module, Class Sum Computation Unit, Probabilistic Classifier, Clause Feedback Generation Module, Pseudo Random Number Generator (PRNG), Weight Update Unit, And Tsetlin Automata (TA) State Update Unit. The PRNG-driven Probabilistic Feedback Mechanism Selectively Reinforces Significant Clauses While Suppressing Less Informative Ones, Enabling Adaptive Clause Learning And Efficient Weight Optimization. Furthermore, Probabilistic Classification And State-transition Strategies Improve Convergence Speed, Enhance Robustness Against Overfitting, And Increase Classification Accuracy. The Resulting PSU-DTM Architecture Provides A Scalable, Hardware-efficient, And Interpretable Machine Learning Framework Suitable For Next-generation FPGA-based Intelligent Systems Requiring Low Latency, High Throughput, And Adaptive Learning Capabilities.

Published:

01-7-2026

Issue:

Vol. 26 No. 7 (2026)

Page Nos:

20-33

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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