Abstract :

Elliptic Curve Cryptography (ECC) Has Become One Of The Most Widely Used Public-key Cryptographic Techniques Due To Its High Security And Smaller Key Size Compared To Traditional Cryptographic Algorithms Such As RSA. However, ECC Operations Involve Complex Arithmetic Computations, Particularly Scalar Multiplication, Which Requires Significant Processing Time And Hardware Resources. To Address These Challenges, This Project Presents A High-Speed FPGA Implementation Of An RSD-Based ECC Processor. The Proposed Architecture Utilizes The Redundant Signed Digit (RSD) Number Representation Technique To Improve Arithmetic Performance And Reduce Carry Propagation Delays During Finite Field Operations. By Employing RSD Arithmetic, Parallel Processing Capabilities Are Enhanced, Resulting In Faster Point Addition And Point Doubling Operations, Which Are Fundamental Components Of ECC Scalar Multiplication. The FPGAbased Implementation Provides A Scalable And Efficient Hardware Platform Capable Of Achieving High-speed Cryptographic Processing While Maintaining Low Power Consumption And Reduced Hardware Complexity. Experimental Results Demonstrate That The Proposed RSD-based ECC Processor Significantly Improves Computational Speed And Throughput Compared To Conventional ECC Implementations. The Design Is Particularly Suitable For Secure Communication Systems, Embedded Devices, Wireless Networks, Internet Of Things (IoT) Applications, And Real-time Cryptographic Systems Requiring High-performance Security Solutions.

Published:

15-6-2026

Issue:

Vol. 26 No. 6 (2026)

Page Nos:

1024-1036

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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