Abstract :

The Fast Fourier Transform (FFT) Is A Fundamental Algorithm In Digital Signal Processing, Widely Used In Communication, Radar, Biomedical Systems, And Image Processing Applications. However, Conventional FFT Architectures Suffer From High Latency, Increased Hardware Complexity, And Inefficient Memory Utilization Due To Repeated Computations And Multiple Processing Stages. This Paper Presents A High-throughput And Memory-efficient Radix-4 FFT Architecture Implemented Using Verilog HDL. The Proposed Design Reduces Computational Complexity By Decreasing The Number Of Stages And Improves Throughput Using Pipelined Processing. Additionally, A Memory Optimization Technique Based On Data Reuse Is Introduced To Minimize Memory Access Operations. The Architecture Is Implemented On FPGA Using Xilinx Vivado, And Performance Is Evaluated In Terms Of Delay, Throughput, And Resource Utilization. Results Show That The Proposed Design Achieves Significant Improvements Compared To Traditional Radix- 2 FFT Architectures, Making It Suitable For Real-time High-speed Signal Processing Systems.

Published:

05-5-2026

Issue:

Vol. 26 No. 5 (2026)

Page Nos:

153-159

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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