Abstract :

This Paper Presents The Design Of An 8-transistor (8T) Approximate Full Adder Using Pass Transistor Logic (PTL) In 32 Nm CMOS Technology, Targeting Low-power And High-speed Applications. By Reducing The Transistor Count And Simplifying The Conventional Full Adder Structure, The Proposed Design Achieves Significant Improvements In Power Consumption, Delay, And Area. The Approximation In Sum And Carry Outputs Enables An Efficient Trade-off Between Accuracy And Performance, Making It Suitable For Error-tolerant Applications Such As Image Processing And Multimedia Systems. The Circuit Is Designed And Simulated Using HSPICE, And Its Performance Is Evaluated In Terms Of Power Dissipation, Propagation Delay, And Power-delay Product (PDP). Simulation Results Indicate That The Proposed 8T Design Offers Superior Energy Efficiency Compared To Conventional Full Adders While Maintaining Acceptable Error Characteristics For Practical Applications

Published:

16-4-1-2026

Issue:

Vol. 26 No. 4-1 (2026)

Page Nos:

590-594

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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