Abstract :

The Rapid Evolution Of Integrated Circuit Technology Has Significantly Increased Design Complexity, Making The Optimization Of Power, Performance, And Area (PPA) A Critical Concern In VLSI Physical Design. Conventional Electronic Design Automation (EDA) Techniques, Which Rely On Rule-based And Heuristic Strategies, Often Struggle To Efficiently Explore Large Design Spaces And Achieve Optimal Trade-offs Between Competing Design Objectives. This Work Introduces An AI-assisted Framework That Enhances Physical Design Processes By Incorporating Machine Learning Techniques Into Stages Such As Floorplanning, Placement, And Routing. Predictive Models Are Developed To Estimate PPA Metrics Using Key Design Parameters, Including Gate Density, Interconnect Characteristics, And Switching Behaviour. These Predictions Are Utilized To Guide Design Optimization Toward More Efficient Layout Configurations. Experimental Analysis On Benchmark Circuits Demonstrates That The Proposed Approach Achieves Noticeable Reductions In Power Consumption And Delay, Along With Improved Area Utilization. Additionally, Hardware Validation Using Verilog Confirms The Practicality Of The Framework. The Results Emphasize The Growing Importance Of AI In Enabling Intelligent, Scalable, And Efficient VLSI Design Methodologies.

Published:

14-4-1-2026

Issue:

Vol. 26 No. 4-1 (2026)

Page Nos:

569-573

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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