Abstract :

Modern Digital Signal Processing, Scientific Computation, And Artificial Intelligence Applications—where Fast Speed And Low Power Consumption Are Critical Design Requirements—all Heavily Rely On Floating-point Multiplication. This Work Describes A Hybrid Booth Encoder-based Floatingpoint Multiplier That Uses CMOS 0.18-µm Technology And Is Both Low-power And Area-efficient. In Order To Minimize Hardware Complexity, The Suggested Architecture Uses A Hybrid Encoding Technique, Processing The Most Significant Bits Using Exact Radix – 4 Booth Encoding Scheme While The Least Important Bits Are Processed Using The Approximate Radix – 8 Booth Encoding Scheme. Microwind Is Used To Implement The Design At The Transistor Level For Performance Evaluation, While DSCH Is Used For Modeling And Functional Validation. When Examined Alongside The Traditional Radix – 8, Radix – 4, And Contemporary Hybrid Architectures, Simulation Results Show Notable Savings In Gate Count, Power Consumption, And Operating Current. The Suggested Multiplier Is Appropriate For Low-power VLSI And Floating-point Processing Applications Since It Achieves Increased Speed And Energy Efficiency While Preserving A Respectable Level Of Computational Accuracy. Keywords— Floating-Point Multiplier, DSCH, Microwind, Low-Power VLSI, CMOS 0.18-µm Technology, Booth Encoding, Hybrid Radix-4/Radix-8, Approximate Computing, And Partial Product Reduction.

Published:

02-4-2026

Issue:

Vol. 26 No. 4 (2026)

Page Nos:

118-124

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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