Abstract :

In Contemporary Digital Communication And Memory Systems, Error Detection And Repair Methods Are Essential To Preserving Data Reliability. The Hamming Code Is One Of The Most Popular Error Correction Methods Because It Can Identify And Fix Single-bit Faults With Little Redundancy. However, Continual Switching Activity In Synchronous Digital Systems Frequently Results In Increased Power Consumption For Typical Hamming Encoder And Decoder Circuits. In Order To Solve This Problem, Clock Gating Techniques Have Been Incorporated Into Current Designs In Order To Lower Dynamic Power By Turning Off The Clock Signal While It Is Idle. Even Though Clock Gating Increases Power Efficiency, Next-generation Low-power VLSI Systems Need More Tuning. The Construction Of A Low-power (7,4) Hamming Code Encoder And Decoder Utilizing Reversible Logic Gates Is Presented In This Study. In Order To Minimize Information Loss And Heat Dissipation While Performing Parity Creation, Syndrome Computation, And Error Correction Operations, The Suggested Architecture Uses Reversible Gates Such As Feynman And Double Feynman Gates. While The Decoder Computes Syndrome Bits To Identify And Fix Single-bit Faults In The Incoming Codeword, The Encoder Uses Reversible Logic Networks To Provide Parity Bits. Verilog HDL Is Used To Implement The Design, And FPGA Synthesis Tools Are Used To Evaluate It. In Comparison To Traditional And Clock-gated Implementations, Experimental Results Show That The Suggested Reversible Logic-based Architecture Provides Lower Power Usage And Propagation Delay. As A Result, The Suggested System Offers A Dependable, Energy-efficient Solution For Contemporary VLSI Communication And Memory Applications.

Published:

27-3-1-2026

Issue:

Vol. 26 No. 3-1 (2026)

Page Nos:

151-156

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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