Abstract :

Multiplication Is A Critical Operation In A Wide Range Of Digital Signal Processing (DSP) Applications, Yet Multipliers Typically Demand Higher Silicon Area, Incur Significant Latency, And Consume Greater Power Compared To Other Digital Building Blocks. To Address These Challenges, Compressor-based Architectures Are Widely Adopted, As Compressors Play A Pivotal Role In The Partial Product Reduction (PPR) Stage By Enabling Parallel Accumulation And Minimizing The Number Of Intermediate Product Terms. This Work Presents An Optimized Compressor Design Integrated Into A Wallace Tree 8-bit Multiplier To Enhance Computational Efficiency. The Wallace Tree Structure, Known For Its Parallel Reduction Capability, Leverages The Proposed Compressor To Achieve Highspeed And Area-efficient Multiplication. Carbon Nanotube Field Effect Transistor (CNTFET) Technology, Derived From Advancements In Fin Field-Effect Transistor (FinFET) Architectures, Is Employed Due To The Superior Electrical Conductivity And Mechanical Strength Of Carbon Nanotubes. The Proposed Compressor Exhibits Reduced Structural Complexity And Better Regularity When Compared With Conventional Designs. The Wallace Tree 8-bit Multiplier Incorporating The New Compressor Is Modeled And Simulated Using Cadence’s Virtuoso Tool With 32 Nm CNTFET Technology. Comparative Simulation Results Demonstrate That The Proposed Design Significantly Reduces Delay And Power Dissipation While Improving Speed, Thereby Outperforming Conventional Wallace Tree And Compressor-based Multiplier Architectures. Keywords—Binary, CNTFET, VLSI And Multiplier

Published:

12-3-2026

Issue:

Vol. 26 No. 3 (2026)

Page Nos:

135-141

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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