Abstract :

This Paper Presents Novel Machine Learning (ML)-based Approximate Arithmetic Circuits, Specifically Focusing On 4-bit Approximate Adders And An 8x8 Approximate Multiplier, Targeting Low-power And High-performance Digital Signal Processing Applications. Two Variants Of 4-bit ML-based Approximate Full Adders (MLAFA-I And MLAFA-II) Are Introduced, Demonstrating Mean Absolute Errors (MAE) Of 1.773 And 1.500 Respectively, Highlighting Their Improved Accuracy Over Traditional Approximate Designs. Building Upon These Adder Units, An 8-bit Approximate Adder Is Constructed Using A Cascaded 4-bit MLAFA Architecture. Additionally, An ML-inspired 6:3 Compressor Is Integrated Into The Design Of An 8x8 Multiplier To Reduce Hardware Complexity While Maintaining Acceptable Computational Accuracy. The Multiplier Evaluation, Conducted Over All 65,536 Input Combinations, Reports An MAE Of 16,685, Reflecting A Trade-off Between Error Tolerance And Hardware Efficiency Suitable For Error-resilient Applications. The Proposed Designs Leverage Majority Gate Logic And Simple Inverters, Resulting In Reduced Circuit Complexity And Potential Gains In Speed And Power Consumption. Simulation Results Confirm The Efficacy Of The Proposed Approximate Arithmetic Units, Making Them Promising Candidates For Approximate Computing In Resource-constrained And Real-time Embedded Systems. Keywords— Machine Learning-based Arithmetic,Majority Gate Logic,Approximate Adder, Approximate Multiplier,Digital Signal Processing (DSP),Mean Absolute Error (MAE),RCA

Published:

28-9-2025

Issue:

Vol. 25 No. 9 (2025)

Page Nos:

716-721

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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