Abstract :

Reversible Computing Offers A Promising Approach To Overcome The Fundamental Limitations Of Conventional CMOS-based Designs, Particularly In Reducing Power Dissipation. This Work Presents A Paper-compliant 1-bit Reversible Arithmetic Logic Unit (ALU) Implemented Using Verilog HDL And Simulated In Vivado. The Design Leverages Parity-preserving Fredkin And CNOT Gates To Execute All 16 Arithmetic And Logic Operations, While Ensuring Single-bit Fault Detection Through A Parity-preserving Mechanism. The ALU Integrates A Reversible Arithmetic Unit, Logic Unit, Control And Selection Module, And A Parity-based Fault Detection Block. The Architecture Is Optimized To Minimize Quantum Cost, Garbage Outputs, And Ancillary Inputs, Achieving A Gate Configuration Of 7 Fredkin Gates And 9 CNOT Gates As Per The Referenced Paper. This Design Demonstrates The Feasibility Of Implementing Fault-tolerant, Low-power Quantum-compatible ALUs With Strict Adherence To Reversible Logic Principles, Paving The Way For Efficient Future VLSI And Quantum Computing Applications. Keywords:Reversible Computing, Fredkin Gate, CNOT Gate, Quantum Cost, Parity Preservation, Fault Detection, Arithmetic Logic Unit, Garbage Outputs, Ancillary Inputs, Low-Power Design, Quantum-Computing.

Published:

27-9-2025

Issue:

Vol. 25 No. 9 (2025)

Page Nos:

686-691

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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