Abstract :

Existing Approximate Booth Multipliers Often Fail To Match The Performance Of Modern Approximate Multipliers, Such As Truncation-based Approximate Logarithmic Multipliers, Particularly In Terms Of Delay And Area Efficiency. This Work Proposes A Novel Decoder Reduction Approximation (DRA) Scheme For Booth Multipliers, Capable Of Operating With Negligible Error Rates While Utilizing Only N/4 Booth Decoders In Place Of The Conventional N/2 Decoders. The Proposed Method Is Fully Optimized For The Booth Algorithm And Is Compatible With All Existing Booth Multiplier Architectures Reported In The Literature. In The DRA Scheme, The Number Of Implemented Decoders Is Reduced, And Boothencoded Signals Are Selectively Filtered Based On Their Percentage Contribution To The Final Product. This Approach Achieves A Significant Reduction In Hardware Resources While Maintaining High Computational Accuracy. The Proposed Multiplier Designs Are Denoted As BD N.W, Where BD Is A Unique Prefix Distinguishing This Work From Prior Designs, N Represents The Bit-width Of The Multiplier (8 Or 16 Bits), And W Specifies The Number Of Decoders. Experimental Evaluation Focuses On Look-Up Table (LUT) Utilization And Combinational Path Delay, Demonstrating That The DRA Scheme Achieves Notable Improvements In Performance And Hardware Efficiency Compared To Conventional Booth Multipliers. Keywords — Decoder Reduction Approximation (DRA) Scheme, Approximate Booth Multiplier, Booth Decoders, Delay, LUT.

Published:

28-8-2025

Issue:

Vol. 25 No. 8 (2025)

Page Nos:

476-480

Section:

Articles

License:

This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.

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